LCD's require an AC drive voltage with virtually no DC component. Prolonged DC operation may cause electrochemical reactions inside the displays which will cause significantly reduced life. The initial indications of display degradation because of excessive DC current is a loss of alignment along the edges of some of the characters. The visual indication will be a "fuzzy" appearance of some of the characters.

Because an LCD is made up of several dielectric layers, the Equivalent Circuit shown below is a series of capacitors and a shunted resistor.

There are also series resistances to consider, including the resistivity of the indium oxide electrode paths and the crossover resistance. The TNFE LCD is an RMS voltage responsive device, that is, the contrast of a given segment is dependent upon the RMS value of the applied voltage across it, measured with respect to the common plane. This fact, which seems obvious now, is very important when discussing drive schemes.

Drive frequencies for direct drive displays are typically between 30Hz and 100Hz. Depending on the display size and design, displays can be operated at higher frequencies, but this will result in increased power consumption. Operation below 30Hz results in display flicker.

LCD's can be overdriven by a combination of voltage and frequency, which will result in cross talk or "ghosting" Ghosting is the appearance or partial activation of an "off" segment. This condition occurs when high drive voltage and frequency are applied. Since the current is directly proportional to the frequency, there is a voltage-frequency product which must not be exceeded. These values are very dependent on the design and layout of any given part, so proper display design and choice of driving conditions is important. It is also very important that all unused segments be connected to the backplane, and not allowed to float.

An actual drive circuit will be a symmetrical square wave with less than 50mV DC offset. The low DC offset drive circuit is best designed using a CMOS "exclusive OR" gate, refer to the bottom part of the figure below:

Please note that normal TTL devices are not suitable for drivers, as they typically have enough DC offset in their output signal to destroy an LCD.

The top part of the above figure shows the output waveforms of our "exclusive OR" circuit. Plot A is the 40 Hz, 50% duty cycle square wave input to the XOR gate, the "clock" signal. Plot B is the control signal waveform which will turn a segment "on". Plot C is the output of the XOR gate, and Plot D shows the RMS voltage as seen by the LCD segment.

Note that when the control input (B) is at logic 0, the resultant output signal to the segment is in phase with the clock output, resulting in a 0V RMS voltage at the segment. It will therefore remain in the "off" state. When the control input to the XOR goes high, the output shifts 180o out of phase to the backplane, resulting in an RMS value at the segment equal to the supply voltage. The segment will turn "on".

The drawing below shows a typical segment plane and common plane layout for a seven segment digit. From the drawing, it can be seen that the common plane electrode is made as large as possible to keep the resistance low and thereby eliminate "ghosting".