Retaining the desirable liquid crystal display characteristics of ultra low power consumption and high contrast ratio under high ambient light levels, multiplexed liquid crystal displays greatly reduce the number of external connections necessary for numeric and mixed numeric descriptor displays and make possible dot matrix displays for full alphanumeric and graphic capability. Unlike conventional LCDs which have separate external connections for each segment and descriptor location plus common plane, multiplexed LCD's have their segments arranged as intersections of an X-Y grid. This reduction in the number of external connections enhances device reliability and potential display density. Their liability is the increased complexity of drive circuitry (or perhaps microprocessor software) necessary for their operation.

Unlike other display technologies that respond to peak or average voltage and current, Liquid Crystal Displays are sensitive to the RMS voltage across the interplane capacitance at a given segment location. In general for a given liquid crystal fluid operating in a multiplex mode, as the number of "common planes" (i.e. electrodes common to all character locations - the "X" dimension of the matrix) is increased, the angle of view over which good display contrast is visible, decreases. When the multiplex rate is greater than about 16, it is necessary to switch to an STN display to maintain viewing angle and contrast. This applications note is applicable to both TN and STN displays, although for simplicity, we will show examples of a segmented display, and a 5x7 dot matrix only.

Three matrix formats have emerged as popular configurations. The 2 x 4 format, shown in Figure 1, is useful in numeric displays utilizing seven segments plus decimal point at each character location. Figure 1(a) shows the interconnections on the common planes. Note that the same segments at each digit are bussed together. Figure 1(b) shows the interconnections of the segment planes, rendering the 2 x 4 matrix arrangement for each character location as illustrated in 1(c). Figure 1(d) shows the method by which four descriptors may be handled as a 1 x 4 subgroup in the same display.

Figure 1

                

Figure 2 below illustrates the 5x7 dot matrix format. Seven common plane rows plus five segment plane columns per character form a 35 dot field which can be used for full alphanumeric capability. With this format, the matrix is physically arranged as a rectangular grid.

Figure 2

Other multiplex formats are possible for application to custom display requirements, consistent with limiting one dimension of the matrix to a practical value, and consistent with that which is possible in the geometric sense, i.e. there must be room to get all of the leads to the edge of the glass without crossing each other. Our technical question "What is Direct Drive? Multiplexing?" shows a simple routing scheme.

The method of drive for multiplexed displays is essentially a time division multiplex with the number of time divisions equal to twice the number of common planes used in a given format. As is the case with conventional LCDs, in order to prevent irreversible electrochemical action from destroying the display, the voltage at all segment locations must be caused to reverse polarity periodically so that zero net DC voltage is applied. This is the reason for the doubling in time divisions: Each common plane must be alternately driven with a voltage pulse of opposite polarity.

Refer to the figure at the right, which is representative of the 2 x 4 format, where the waveforms required for the generation of character "4" are given. In (a), (b), (c), and (d) the invariant common plane drive waveforms are shown. They can be thought of as bipolar strobe or select pulses. The segment plane waveforms corresponding to the specific characters "4" are presented in (e) and (f). The algebraically summed voltage at segment locations a, b, c, and d.p. for on and off optimized voltages are shown at (g), (h), (i), and (j), respectively (Refer to figure 1). Voltage level VB is the datum reference for the display. To meet the symmetry criterion, no net DC voltage on the display, note that: (1 )   (VD - VB) = - (0-VB) (1a)   VB = VD/2 (2)    (VC - VB) = - (VA - VB). This convention of voltage levels is chosen consistent with the requirement that the display be driven from a logic system. (CMOS, capable of switching analog voltage levels) operating from a unipolar supply of magnitude >= VD.

To determine the optimum ratio of (VD - VB) to (VC - VB), or identically (0 - VB) to (VA - VB), requires analysis of the mathematical expressions for the net RMS voltages impressed upon segment locations for both the on and off conditions.

In general, for a multiplexing scheme of N common planes and the conventions specified above:

Optimum display contrast will occur when the ratio of the above expressions is maximized. This is determined by setting the derivative of the RMS ratio equal to zero and solving for VC in terms of VD. Our technical question "What is Contrast" shows how contrast is measured. Applying the formulae:

Substituting equation (7) into equations (3) and (4) provides expressions for optimized RMS on and off voltages:

Figure 4 at left is a histogram plot showing normalized values of VRMSon and VRMS off (i.e. VD = 1.000) showing the interdependence of available drive voltage and the number of common planes. Note that as the number of common planes is increased, the contrast versus voltage requirement for the liquid crystal fluid used in such a format becomes more stringent. To actually use a given liquid crystal fluid in a given multiplex format requires matching of the fluid's turn on threshold voltage to the drive system's RMS off voltage. Utilizing equation (8a) by substituting the liquid crystal fluid's threshold voltage for VRMS Off will specify a minimum value of VD and thus a minimum supply voltage for the driving logic.

Figure 5 below shows a typical voltage divider network suitable for providing the analog voltage levels to a multiplexed display via CMOS analog switching. Resistors RA, RB, RC and RD set the voltage ratios. Potentiometer RE sets the magnitude of VD to match the liquid crystal requirements. Capacitor Cbypass insures that node VD is of low source impedance at the drive frequency (i.e. at fdrive XC << RD), providing symmetric source impedances at the taps of the divider. Under these conditions the highest impedance tap is at VB and is approximately equal to:

As is the case with non multiplexed displays, the drive frequency should be chosen to be above the flicker-fusion rate, i.e. >30 Hz. Since increasing the drive frequency significantly above this value increases current demand by the CMOS drive electronics, and to prevent problems due to the finite conductivity of the display segment and common electrodes, an upper drive frequency limit of 60-90 Hz is recommended. With these frequency limits in mind, the approximate source impedance of the divider network can be determined as a function of the net capacitance of the display to be driven. Because this capacitance is a function of the dielectric anisotropy of the liquid crystal fluid, it is non-linear with voltage and should be taken at its maximum value for the fully "on" condition.

Since the exact loading at each divider network voltage tap is a complex function of the instantaneous common plane drive, segments energized, and segments unenergized, the following rule of thumb is suggested as a method of choosing appropriate network source impedances. The RC time constant formed by the source impedance of node VB and the total "on" capacitance of the display should be an insignificant fraction (e.g. < 1/100) of the common plane pulse width.

Recalling equation (10), the rule of thumb becomes:

For example: let

N = 3 (e.g. 3 x 3 format), fDrive = 40Hz (suggested nominal), Con = 3.8 nf, VTH = 2.3 VRMS ( LC fluid threshold)

As is the specification for non-multiplexed displays, the net DC component to which a segment location can safely be subjected is <50mV. A worst case analysis of resistor tolerances shows that if RA, RB, RC and RD are 1% film units, the criterion is met.

If a multiplexed LCD is to be operated over a temperature range in excess of the normal indoor ambient range of 18oC to 25oC, temperature compensation such that VRMSoff tracks the fluid threshold voltage Vth, may be required. Depending upon the particular liquid crystal fluid, the temperature coefficient of Vth is typically in the range of -5 to -15 mV/oC. Re-inspection of equation (8a) shows the relation between the temperature coefficient of VRMS "OFF" and that of VD: The right hand term of equation (8a) must be multiplied by the temperature coefficient of Vth to determine the temperature coefficient of VD. Note that this resultant is dependent upon the particular multiplex format utilized.

Thus, in summary, considerations of:

are the constituents of the successful application of multiplexed LCDs.

At this writing for multiplex rates up to about 16, LXD recommends use of type #3 fluid for multiplex operation. This fluid features wide operating temperature range, good contrast versus voltage characteristic and moderate temperature coefficient.

Figure 6 below shows the contrast versus voltage relationship for our type #3 fluid operating in the reflective mode at 20oC. Contrast is normalized (i.e. 0 to 100%) and viewing angle is normal to the display. Notation on the curve shows operating points for multiplex operation with the threshold voltage set to recommended 2.30 VRMS @ 20oC  in all cases, and the corresponding RMS "ON" voltages for N = 2 through N = 8, inclusive, where N is the number of common planes used in the multiplex format.

Figure 6

The threshold voltage for liquid crystal fluids is temperature dependent. LXD's #3 fluid, in the range of -20oC to + 60oC, has a linear slope of -8.0 mV/oC.  This coefficient must be multiplied by the appropriate factor for the particular multiplex format under consideration.

Table A below presents electrical specifications for LXD #3 fluid.. The capacitance specifications are total device capacitances, with all segments tied in parallel.

Advanced Multiplex Derivation

Let us assume a matrix arrangement of segments N x m. In the drawing on the right, the horizontal lines labeled CP1, CP2, etc represent the common planes of a display multiplexed by N, and the vertical lines labeled SEG1, SEG2, etc, represent the N segments in the display.

Let us further assume a time division scheme whereby time sequential "select" or "strobe" pulses are applied to the common planes (N dimension of matrix) at some arbitrary amplitude Vs. Refer to drawing on left. On the segment lead, we place an arbitrary voltage +/- VD, so that when it is summed with strobe pulse Vs sum (VS + VD) causes a segment location to turn on, and sum (VS-VD) causes a segment location to turn off. Refer to drawing on right. Symmetric levels +/- VD are chosen as a consequence of the (N -1) time intervals when the strobe pulse is not present. If asymmetrical levels are chosen, a higher residual voltage will be present on unaddressed segments.

Twisted nematic liquid crystals are RMS sensitive. RMS voltage is proportional to the power that a voltage waveform can impart to its load:

The net RMS voltage seen by segment locations within the display can be calculated:

The optimum drive situation occurs when the above expressions achieve their maximum ratio. A little differential calculation is used to determine this maximum, which will yield:

The above scheme will impart DC voltage to the LCD. To correct this, all voltage polarities are inverted on alternate scans. In the timing diagram on the top left, the common plane voltage is shown to reverse polarity every N timing divisions. The resulting net DC voltage over a complete cycle is therefore 0V. In the segment waveform shown at the bottom left,  the voltage applied to a given segment is somewhat more complicated because multiple segment drive signals are present. Our segment will only be turned on when the two waveforms are combined, and the resultant total RMS voltage exceeds the threshold voltage of the fluid used.

An alternate and functionally identical scheme is also used wherein the alternate polarity pulse pairs are applied in each scan through the commons. These waveforms are essentially the same as in the above example except that the positive and negative pulses occur during consecutive clock cycles. The resultant DC voltage is still 0V. The display segment still turns on during periods where the total RMS voltage is greater than the threshold voltage of the fluid, which now happens on successive clock cycles.

Maximum drive potentials are most easily generated with a CMOS logic structure. Most CMOS structures require voltage levels that they control to be constrained to level between their supply rails. Most CMOS logic systems are designed to operate on a single positive supply in the range of 3 to 18 volts. A large proportion of systems operate at a supply voltage of 5 volts, the standard for virtually all computers and microcomputers based in TTL and NMOS technologies. Some advanced CMOS structures allow for level translation, i.e. adapting a CMOS display driver to operate at a higher supply voltage than the main system.

	Because of these constraints, level shifting is applied to the bipolar waveforms discussed above. In the most basic form, a constant voltage of magnitude VS is added to all voltage levels, shifting them to the range 0 to + 2VS, which is compatible with the drivers:

In a more advanced form, level shifting in an amount equal to VD is applied during the intervals when the strobe pulses are positive and in an amount equal to VS when the strobe pulses are negative. This system requires one additional voltage level but provides a real economy of overall supply voltage, reducing it from 2VS to VS + VD. This can be a 20 to 35% reduction depending on N.

In all the above systems the voltage levels required are obtained from a resistive voltage divider. These resistors may be chip external making the system reconfigurable for different N's, if the driver is also reconfigurable. The resistors may also be internal to the chip . The taps off the resistive divider are controlled and switched to the display electrodes by a structure known interchangeably as an analog switch, a bilateral switch or a transmission gate. These act as an interfaces between the normal logic level control signals and the analog levels applied to the display. See our "Multiplexing Liquid Crystal Displays" app note for a discussion of these divider networks.

The supply voltage required for a given system depends on the LC threshold voltage, N, and the level shifting system used. The expression for the RMS off voltage must be made to match the threshold voltage of the LC fluid. Since the LC threshold voltage has a specific temperature coefficient, the overall supply voltage must be adjusted to track this temperature compensation for wide temperature excursions. The RMS "OFF" voltage in a given system is some constant fraction of the overall supply voltage. Since this fraction must track the LC threshold voltage, the temperature compensation of the threshold voltage must be multiplied by the inverse of the fraction to determine the ultimate temperature compensation of the supply voltage.

Temperature sensing is most easily accomplished with a sensor with a linear characteristic . A small buffer amplifier is generally required to interface the sensor to the output provisions in the display driver. Depending on those provisions, the buffer amp may need to feed the + or - chip power supply or + or - end of the resistive divider.

Due to the contrast versus voltage versus temperature characteristics of liquid crystal fluids and the sensitive nature of display drive voltage during multiplex operation, it becomes necessary to compensate LCD drive voltage for applications where the display is subjected to wide temperature excursions. For a typical twisted nematic liquid crystal fluid with a negative temperature coefficient, an under voltage condition with diminished display contrast will result at low temperatures and a "ghosting" or over drive condition will occur at high temperatures if no compensation techniques are employed. That which follows is a discussion of a practical method of providing first order linear compensation, compatible with most available driver circuits. Two examples are presented.

The first thing that needs to be determined in a particular application is the relationship between display RMS "OFF" voltage end display driver circuit supply voltage. Since different drive schemes are utilized, e.g. 3, 4, and 5 voltage level drive arrangements, this is best determined from the manufacturer's data sheet. Also required are the temperature coefficient and threshold voltage of the liquid crystal fluid. The fluid temperature coefficient must be divided by the ratio of RMS "OFF" voltage to driver circuit supply voltage to calculate the ultimate temperature coefficient of the driver circuit supply voltage. In this way the display RMS "OFF" voltage will track its optimum value over the temperature range.

Figure 7 below shows the basic temperature regulation circuit. The heart of the circuit is U1, a National Semiconductor LM335 monolithic temperature sensor, which should be placed in physical contact with the LCD. The LM335 has a basic output voltage coefficient of 110mV/oC. Resistor R2 supplies operating current to U1, 1 mA nominal. Difference amplifier U2 inverts and scales this coefficient consistent with LCD/driver requirements. Potentiometer R1 provides a means by which the display operating voltage can be set. Note that range limiting resistor R1' and R1" may be added to increase the resolution of R1 and to determine suitable end points. Operational amplifier U2 may be any type capable of supplying sufficient output current to power the display driver circuit(s). An LM307 is a good choice for small systems since its output can swing close to the supply rail, minimizing the magnitude of the positive supply required. R1 must be fed from a regulated supply to maintain a stable output voltage at U2.

Figure 7

EXAMPLE #1

This drive uses the basic "1/2 select" scheme (4 voltage levels and reference as described earlier). As such, the display RMS "OFF" voltage is .211 times the overall driver supply voltage, for n = 7. The temperature coefficient of the supply voltage can be calculated:

The driver supply voltage at the temperature limits can be computed from the display threshold voltages at those limits:

Referring to Figure 8 below, let R3= 10K, then R4 = 39K to determine the proper temperature coefficient at the output of U2. From the specifications of the LM335 device, it is found that its output voltage is 2.98 +/- .06 volts at 25oC. Using the basic op amp closed loop gain equation:

VR1 should be in the range of 3.95 to 4.05 volts considering the tolerance of U1. Choosing R1 =5K, R1' = 39K, and R1" = 18K allows VR1 to be varied +/- .5 volts, which is more than sufficient range. Since U2 must swing to +9.2 volts output at the low temperature limit, its positive supply is chosen at +12 volts. R2 can now be determined to be ~10K to allow 1 mA nominal current flow into U1. Also shown in Figure 9 is a method of level translation from standard 5 volt logic to the temperature controlled voltage of the drivers. U3, an RCA CD40109, low to high voltage converter, translates the incoming control signals. U4A, one-sixth of a CD4060 buffer, allows a high to low voltage logic conversion for the interrupt line feeding back to the main system.

Level conversion by returning VSS to a negative voltage is suggested in the HLCD 0638/0539 data sheet. If the input is assumed to be standard 5 volt logic (HLCD 0538/0539 VDD terminals tied to +5 volts), VSS may go as negative as -1.67 volts before input logic level constraints are violated. This net driver circuit supply voltage of 6.67 volts maximum corresponds to a display temperature of 56.7oC minimum, clearly an unacceptable constraint.

EXAMPLE #2

This family of drivers uses the "1/3, select" format of multiplex drive (3 voltage levels and reference). As shown in the Intersil data sheet, the display RMS "OFF" voltage is .333 times the overall driver internal resistor string voltage. Note that the negative end of the resistor string is brought out separately from the device's VSS terminal. The temperature coefficient of the display supply voltage can be calculated:

The display supply voltage at the temperature limits can be computed from the display threshold voltages at those limits:

Figure 9 at left shows a modified form of the basic temperature compensation circuit in which U1 and R2 are reversed in position. This inverts the sense of voltage VTEMP so that the out put of U2 goes more positive with increasing temperature to accommodate feeding the negative end of the display drive divider string. Resistor R3 is once again assumed at 10K, this time rendering R4 at 24K to match the required display voltage temperature coefficient. Recalling the resolved op amp closed loop gain equation from the previous example, VR1 is found to be in the range of 1.39 to 1.47 volts, taking into account the LM335 output voltage tolerance. Choosing R1 = 5K, R1' = 15K and R1" = 47K provides more than adequate adjustment range.

Note that at the low temperature design limit the overall display divider supply voltage goes to 5.34 volts The driver data sheet states that the voltage at terminal VDISP must not go any more negative than 0.3 volts below system ground (VSS). If this driver is operated from a standard 5 volt logic system, this indicates a small discrepancy (.04 volts) in the display divider supply voltage raising the minimum acceptable low temperature limit to + 11.7oC at specification. If lower temperature operation is contemplated using this family of drivers, the more elaborate level shifting scheme utilizing the CD40109 is required to keep the drivers within their specifications.