LCD Module Protocol Interfaces | LXD Research & Display

LCD controllers use familiar interfaces. Some controller ICs have more than one interface option that is user selectable. In many cases, the module LXD supplies to you will already be internally configured to your interface requirements. As an LCD module manufacturer, LXD welcomes discussions about various module design parameters, including different interface options.

All interface protocols must initialize the LCD module when it is first energized prior to use.

The most common LCD Module Interface Protocols are:

1. Parallel Interface

The parallel interface typically controls the LCD via 8 data pins and 3 control lines. The control lines used are Enable (E), Register Select (RS), and Read/Write (R/W).

RS tells the LCD module if the information being sent is an Instruction or Data. The

Enable tells the LCD module that the data or instruction in the register is ready to be interpreted by the LCD Module. Some controllers may have more than one Enable Control Line. The Read/Write tells the module whether to write data or read data from the register.

In addition to the common interface connections presented as examples here, some modules may include additional control lines. Some examples are:

V0 - Contrast Adjustment, which adjusts the voltage applied to the LCD

CS - Chip Select

BUSY - Typically a low state indicates busy state

Parallel Interface Types

16 Bit Data - Not Common - used on some graphic controllers
8 Bit Data - Most Common - used on graphic and character controllers
4 Bit Data - Used on some monochrome QVGA modules. An option on character controllers
8080 type - Parallel Data with Write Line, Read Line
6800 type - Parallel Data, with Read/Write Line, Enable Line

Some parallel interface connection examples are:

8-Bit Parallel

Designation	Description	Function
RS	Register Select	Control line L: Instruction H: Data write
R/W	Read/Write	Control line L: Data Write, H: Data Read
E	Enable	Control line - Allows information to be interpreted
D0	Data Line	8 Bit Parallel Data Lines
D1	Data Line
D2	Data Line
D3	Data Line
D4	Data Line
D5	Data Line
D6	Data Line
D7	Data Line

4-Bit Parallel (Common for QVGA monochrome display modules)

Designation	Description	Function
FLM	First Line Marker	Control line - Frame Signal
DISP OFF	Display Off	Control line L: Display Off, H: Display On
M		Control line - AC signal for Display Driver
CL1, LP	Latch Pulse	Data Latch Clock Signal
CL2, CP	Shift Pulse	Data Shift Clock Signal
D0	Data Line	4 Bit Parallel Data Lines
D1	Data Line
D2	Data Line
D3	Data Line

2. Serial Interface

Serial Interface Types

o Serial - Serial Data In, Register Select, Reset, and Serial Clock

Custom - Various configurations - Add Latch, Chip Select

o SPI (Serial Peripheral Interface)

SPI (3 wire) uses Serial Data Out, Serial Data In, and Serial Clock
SPI (4 wire) adds Chip Select
Custom - Various configurations - Serial Data, Serial Clock, Latch, Chip Select

Timing and operation may differ from usual SPI

o I²C (Inter-Integrated Circuit) - Uses Serial Data Line and Serial Clock

Some interface connection examples are:

Serial

Serial LCD controllers typically have one Serial Data Line that writes data and cannot read. Normally, a Register Select Line (Sometimes designated A0) is used to tell the controller whether the incoming data is display information or a controller command

Serial interface example

Designation	Description	Function
SCL, SCLK, SCK, or CLK	Serial Clock	Control line (output from master)
CS, CSn (n = chip selected, "1, 2, etc")	Chip Select	Control line L:Chip Selected, H:Unselected
SDI, DI, SI, SDA	Serial Data In	Data Line
A0	Register Select	H: Data, L: Instruction
RES	Reset	L: Enable, H: Disable

When RES is enabled, the register settings are initialized or cleared.

SPI Interface

SPI, or Serial Peripheral Interface bus, is a synchronous (data is synchronized to the clock) serial data link standard that operates in full duplex mode, which means that devices that can communicate with one another simultaneously. To do this, two data lines are required. With this standard, devices communicate in a master/slave mode, where the master device (host processor) initiates the data and the clock. The LCD module is the (or one of the) peripheral slave device(s) attached to the data bus. Multiple peripherals (display modules and other devices) are addressed on the same serial data bus. However, the LCD module will only listen to the data it sees when the Chip Select line is active (usually low). If the Chip Select line is inactive (usually High), the LCD module listens to the data on the bus, but ignores it. The SDO line is not active when this state occurs.

The SPI bus is comprised of four logic signals, two control lines and two data lines and is commonly referred to as SPI (4 wire).

Serial SPI interface example

Designation	Description	Function
SCL, SCLK, SCK, or CLK	Serial Clock	Control line (output from master)
CS, CSn (n = chip selected, "1, 2, etc")	Chip Select	Control line (not present for SPI 3-wire)
SDI, DI, SI	Serial Data In	Data Line
SDo, DO, SO	Serial Data Out	Data Line

Occasionally, SDI (serial data in) may be called out as MOSI (Master Out Slave In) from Motorola's original name for these lines and MISO (Master In Slave Out) for SDO. The chip select line may be alternatively labeled SS (Slave-Select), or STE (Slave Transmit Enable). SPI is sometimes referred to as National Semiconductor's trademark Microwire, which is essentially a predecessor of SPI, which only supports half duplex.

With CS (Chip-Select) the corresponding peripheral device is selected by the LCD Controller. This pin is mostly active-low. In the unselected state the SDO lines are hi-impedance and therefore inactive. The clock line SCL is brought to the device whether it is selected or not. The clock serves as synchronization of the data communication.

The chip select signal CS is optional for a single device system, because you could tie the CS input at the LCD Module low, if the other lines are dedicated to SPI use. This is sometimes called a 3 Wire SPI Interface.

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SPI Data transmissions usually involve two shift registers. Most display module applications normally use 8-bit words. However, different size words, such as 12 bit, are also used. By convention, the most significant bit is shifted out of one shift register while the least significant bit is shifted in. The word is then written into memory if the CS (chip-select) is low (active). If not, the data is ignored.

Since the SPI interface protocol is a de facto standard, many variations of the standard protocol are used. For instance, chip manufacturers may use some of the parallel data lines when configuring the IC driver chip for serial communication.

I²C (Inter-Integrated Circuit)

I²C uses only two bi-directional lines, Serial Data Line (SDA) and Serial Clock (SCL), which are both typically pulled up with resistors. Typical voltages used are +5 V or +3.3 V. One of the strengths of the I²C interface is that a micro can control multiple devices with just the two I/O pins and software.

Because of the I²C design, it is only half-duplex. The interface generally transmits 8-bit words, sending the most significant bit first.

RS232 Interface :

The RS232 serial interface uses 3 lines to control the LCD module. These are transmit, receive, and ground. This interface does not require the Enable and Register Select lines.

3. Serial or Parallel Configuration to Microprocessor

Some modules may include additional control lines. Some examples are:

C86 - Defines specific MPU interface. For instance, H: 6800, L: 8080

CS - Chip Select. For instance, H: Chip Unselected, L: Chip Selected

Designation	Description	Function
RST, RES	Reset	Control line L: Settings initialized
E1	Enable 1	Control line - Allows Read/Write information to be interpreted
E2	Enable 2	Control line - Allows Read/Write information to be interpreted
R/W	Read/Write	Control line L: Data Write, H: Data Read
A0/DI	Register Select / Data In
D0	Data Line	8 Bit Parallel Data Lines
D1	Data Line
D2	Data Line
D3	Data Line
D4	Data Line
D5	Data Line
D6/SCL **	Parallel mode Data Line/ Serial Clock
D7/SDI **	Parallel mode Data Line/ Serial Data In

**Chip manufacturers will assign different functions to a specific bus connection, depending on whether the chip is configured for Parallel or Serial.

4. TFT Interface Examples

TFT Parallel Interface

Designation	Description	Function
DCLK, CK	Data Sampling Clock	Control line Data Sampling Clock Signal
HSync	Horiz Sync signal	Control line - Horizontal Sync Signal (negative going)
VSync	Vertical Sync Signal	Control line - Vertical Sync Signal (negative going)
R0	Red Data Signal	Data Lines
R1	Red Data Signal
R2	Red Data Signal
R3	Red Data Signal
R4	Red Data Signal
R5	Red Data Signal
GND	Ground	Ground lines are placed between various signal lines for isolation. Only 3 shown as examples
G0	Green Data Signal	Data Lines
G1	Green Data Signal
G2	Green Data Signal
G3	Green Data Signal
G4	Green Data Signal
G5	Green Data Signal
GND	Ground
B0	Blue Data Signal	Data Lines
B1	Blue Data Signal
B2	Blue Data Signal
B3	Blue Data Signal
B4	Blue Data Signal
B5	Blue Data Signal
GND	Ground
ENAB	Enable	Control line - Horizontal Display Position Set Signal H: Enables LCD
R/L Option may not be present	Right or Left Scan	Chip Specific - tied to V_CC or GND
U/D Option may not be present	Up or Down Scan	ChipSpecific - tied to V_CC or GND
V/Q Option may not be present	VGA or QVGA	Chip Specific - tied to V_CC or GND

Digital 18-Bit RGB-TFT Interface with Gamma Correction

Designation	Description	Function
DCLK	Clock Signal Input	Control line H: User can input different polarity CLK by EDGSL Setting L: User can select CLK Rising or Duel Edge to Latch by EDGSL
EDGSL	Define Input Clock Polarity	Control Line L: Latch Data by Rising Edge of CLK (Default) H: CLK Polarity is Inverted, Latch Data by Falling Edge of CLK
VCC	Digital Power Supply	3.3V Typical
AVDD	Analog Power Supply
RESETB	Hardware Global Reset	L: Active, H: Default Pull High
VGL	Gate Off	Control line - Gate Off Power Supply Voltage
VGH	Gate On	Control line - Gate On Power Supply Voltage
VCOM	Common Voltage	Common Electrode Voltage Input
V1	Gamma Voltage level 1
V2	Gamma Voltage level 2
V3	Gamma Voltage level 3
V4	Gamma Voltage level 4
V5	Gamma Voltage level 5
V6	Gamma Voltage level 6
V7	Gamma Voltage level 7
V8	Gamma Voltage level 8
V9	Gamma Voltage level 9
V10	Gamma Voltage level 10
DE	Input Data Enable Control	When in DE mode, Active high to enable data input, Default Pull Low.
R0 (LSB)	Red Data Signal	Data Lines
R1	Red Data Signal
R2	Red Data Signal
R3	Red Data Signal
R4	Red Data Signal
R5 (MSB)	Red Data Signal
GND	Ground	Ground lines are placed between various signal lines for isolation. Only 3 shown as examples
G0 (LSB)	Green Data Signal	Data Lines
G1	Green Data Signal
G2	Green Data Signal
G3	Green Data Signal
G4	Green Data Signal
G5 (MSB)	Green Data Signal
GND	Ground
B0 (LSB)	Blue Data Signal	Data Lines
B1	Blue Data Signal
B2	Blue Data Signal
B3	Blue Data Signal
B4	Blue Data Signal
B5 (MSB)	Blue Data Signal
GND	Ground

TTL-TFT Interface

Designation	Description	Function
DCLK, CK	Data Sampling Clock	Control line - Latch Data At Negative Edge Signal
R0 (LSB)	Red Data Signal	Data Lines
R1	Red Data Signal
R2	Red Data Signal
R3	Red Data Signal
R4	Red Data Signal
R5 (MSB)	Red Data Signal
GND	Ground	Ground lines are placed between various signal lines for isolation. Only 3 shown as examples
G0 (LSB)	Green Data Signal	Data Lines
G1	Green Data Signal
G2	Green Data Signal
G3	Green Data Signal
G4	Green Data Signal
G5 (MSB)	Green Data Signal
GND	Ground
B0 (LSB)	Blue Data Signal	Data Lines
B1	Blue Data Signal
B2	Blue Data Signal
B3	Blue Data Signal
B4	Blue Data Signal
B5 (MSB)	Blue Data Signal
GND	Ground
DE	Data Enable	Control line - Horizontal Display Position Set Signal H: Enables LCD

SPI-TFT Interface

Designation	Description	Function
SCL	Serial Clock	Control line SPI Serial Interface Clock
HSync	Horiz Sync signal	Control line - Horizontal Sync Signal (negative going)
VSync	Vertical Sync Signal	Control line - Vertical Sync Signal (negative going)
RES	Reset	Reset Enable
CS	Chip Select	SPI Chip Select
SDO	Serial Data Out	SPI Serial Data Output
SDI	Serial Data In	SPI Serial Data Input
ENAB	Enable	Control line - Horizontal Display Position Set Signal H: Enables LCD
DCLK, CK	Data Sampling Clock	Control line Data Sampling Clock Signal
R0	Red Data Signal	Data Lines
R1	Red Data Signal
R2	Red Data Signal
R3	Red Data Signal
R4	Red Data Signal
R5	Red Data Signal
GND	Ground	Ground lines are placed between various signal lines for isolation. Only 3 shown as examples
G0	Green Data Signal	Data Lines
G1	Green Data Signal
G2	Green Data Signal
G3	Green Data Signal
G4	Green Data Signal
G5	Green Data Signal
GND	Ground
B0	Blue Data Signal	Data Lines
B1	Blue Data Signal
B2	Blue Data Signal
B3	Blue Data Signal
B4	Blue Data Signal
B5	Blue Data Signal
GND	Ground

LVDS (Low-Voltage Differential Signaling)

LVDS is a differential signal system that is typically used for high speed data rate transfer. LVDS is not an interface protocol, but rather the hardware mechanism that is used to transmit the data across wires. This system can be used with either serial or parallel or a hybrid interface protocol.

The operation basically has the LCD controller transmitting two logic voltage levels that are compared in the LCD module. LVDS uses the difference in voltage between the two lines to encode information. These two lines are typically twisted pairs. The transmitter sends a small current into one line or the other, depending on the logic level to be sent. The current passes through a resistor which is matched to the impedance of the line at the LCD module, then returns in the opposite direction along the other wire. The LCD module senses the polarity of the voltage across the resistor to determine the logic level.

This type of signal minimizes the amount of radiated electromagnetic noise and power lost to conductor resistance. LVDS is less susceptible to noise than single wire data systems because it uses two wires with opposite current/voltage swings instead of the one wire used in single-ended methods to convey data information. The advantage of the differential approach is that if noise is coupled onto the two wires, the noise appears on both lines equally, and is mostly self-cancelling. The op amp at the receiver/LCD module end basically only looks at the difference between the two signals. Using this differential convention, the signals also tend to radiate less noise than single wire data signals due to the canceling of the induced magnetic fields. Constant current drivers are also not prone to ringing or switching spikes, which further reduces noise.

How LVDS Works

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The schematic diagram shows a simple LVDS driver and receiver. It consists of a current source that drives the differential pair lines and an op amp receiver with high input impedance. This causes most of the driver current to flow through the termination resistor, which generates a voltage across the receiver inputs. When the driver switches, it changes the direction of current flow across the resistor, which changes the voltage sense from positive to negative, which creates a logical "one" or "zero".

TMDS (Transition Minimized Differential Signaling)

TMDS is a technology for transmitting high-speed serial data and is used by the DVI and HDVI video interfaces.

TMDS is similar to low-voltage differential signaling (LVDS) in that it uses differential signaling to reduce electromagnetic interference (EMI), which allows faster signal transfers with increased accuracy. Like LVDS, the data is transmitted serially over the data link.